The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system capable of completely cutting off a current flowing to and from the outside when a supply of a power source voltage is stopped.
Among one-chipped semiconductor integrated circuits and semiconductor integrated circuit systems having a plurality of such semiconductor integrated circuits provided on the same one printed circuit board, some of them are equipped with means for stopping a power source of a part of the semiconductor integrated circuits in order to eliminate power that is consumed in non-operating circuit portions. Particularly, it is essential that such means are loaded onto the semiconductor integrated circuits or the semiconductor integrated circuit systems that are operated by batteries as their power source.
FIG. 11 is a block diagram showing a schematic configuration of a conventional representative semiconductor integrated circuit system. In FIG. 11, a semiconductor integrated circuit system has peripheral ICs 1 to 3, a CPU 4 and a memory 5 structured as a plurality of semiconductor integrated circuits. Particularly, these semiconductor integrated circuits carry out data input/output via a bus 6 pulled up to a high power source voltage by a pull-up resistor 7.
In the system having this structure, it is not necessary to keep the peripheral ICs 1 to 3 operated at all times. Therefore, the power supply to all or a part of the peripheral ICs 1 to 3 is cut off during a specific period, thereby to save power.
FIG. 12 is a diagram for explaining the operation of a signal output circuit of the conventional peripheral IC. In FIG. 12, a peripheral IC1 has a power source terminal 200 and an output terminal 201 connected to a data bus 6. Inside this peripheral IC1, there is provided a signal output circuit that consists of a PMOS transistor 202 having its source connected to the power source terminal 200 and its drain connected to the output terminal 201, an NMOS transistor 203 having its source grounded and its drain connected to the output terminal 201, a NAND gage 204, an NOR gate 205, and an inverter 206.
The NAND gate 204 inputs an output enable signal to one input terminal, inputs output data to the other input terminal, and connects an output terminal to the gate of the PMOS transistor 202. The inverter 206 inputs the output enable signal, and applies its inverted output to one input terminal of the NOR gate 205. The NOR gate 205 has an input of the above output data to the other input terminal, and connects its output terminal to a gate of the NMOS transistor 203.
Based on the above structure, this signal output circuit operates as follows. When the output enable signal is at low logical level (hereafter logic level xe2x80x9cLxe2x80x9d), the PMOS transistor 202 and the NMOS transistor 203 are both turned OFF. In other words, a signal output from the output terminal 201 of the peripheral IC1 becomes in an undefined state regardless of the logic level of the output data. On the other hand, when the output enable signal is at high logical level (hereafter logic level xe2x80x9cHxe2x80x9d) and also when the output data is at the logic level xe2x80x9cHxe2x80x9d, the PMOS transistor 202 becomes in the ON state and the NMOS transistor 203 becomes in the OFF state. Therefore, a potential equal to the power source voltage supplied to the power source terminal 200 is applied to the output terminal 201, and the logic level xe2x80x9cHxe2x80x9d is output.
Further, when the output enable signal is at the logic level xe2x80x9cHxe2x80x9d and also when the output data is at the logic level xe2x80x9cLxe2x80x9d, the PMOS transistor 202 becomes in the OFF state and the NMOS transistor 203 becomes in the ON state. Therefore, the potential of the output terminal 201 becomes equal to the ground potential, and the logic level xe2x80x9cLxe2x80x9d is output. In other words, when the output enable signal is at the logic level xe2x80x9cHxe2x80x9d, a signal of the logic level shown by the output data is output straight from the output terminal 201 via the drain to which the PMOS transistor 202 and the NMOS transistor 203 are mutually connected.
FIG. 13A is a circuit diagram, and FIG. 13B is a layout cross-sectional diagram of the PMOS transistor that constitutes a signal output circuit in a semiconductor integrated circuit and other PMOS transistor both of which are supplied with a power source voltage by a common power source, in the conventional peripheral IC. As shown in FIG. 13A, the PMOS transistor 202 that constitutes the signal output circuit has its source connected to the power source terminal 200. This power source terminal 200 is also connected to other PMOS transistor 313 that constitutes a circuit other than the signal output circuit.
In other words, the power source terminal 200 is usually connected to many MOS transistors as a common power supply portion for all circuit blocks within the semiconductor integrated circuit. FIG. 13B shows this relationship as a layout cross-sectional diagram.
As shown in FIG. 13B, the PMOS transistors 202 and 313 are formed in a common N-well area 301 on a P-type semiconductor substrate 300. The PMOS transistor 202 has a drain and a source formed by P-diffusion areas 306 and 307 respectively, has a back gate formed by an N-diffusion area 305, and has the output terminal 201 and the drain electrically connected to each other by an aluminum wiring 312. The wiring of a gate 308 is omitted from the drawing.
The PMOS transistor 313 has a source and a drain formed by P-diffusion areas 302 and 303 respectively, has a back gate formed by an N-diffusion area 304, and has a wiring drawn from the drain by an aluminum wiring 310. The wiring of a gate 309 is omitted from the drawing. The source and the back gate of these PMOS transistors are connected to each other by a common aluminum wiring 311. This aluminum wiring 311 is connected to the power source terminal 200.
When the supply of the power source voltage has been cut off for energy saving as described above, this means that the power supply to the peripheral IC1 has been cut off by turning OFF a power supply switch 100 as power supply control unit in FIG. 12. However, when the power supply has been cut off in this way, the potentials of all the nodes inside the peripheral IC1 become in an unpredictable state (a high impedance state). In other words, it becomes impossible to guarantee the state of the output voltage of the NOR gate 205 in FIG. 12, and the NMOS transistor 203 is not completely turned OFF.
In the state that the power supply has been cut off as described above, the data bus 6 connected to the output terminal 201 is generally pulled up to the logic level xe2x80x9cHxe2x80x9d by the pull-up resistor 7. Therefore, there has been a problem in that unnecessary leakage current flows into the peripheral IC1 from this data bus 6 via the NMOS transistor 203 that has been turned OFF in not a completely OFF state.
This means that, in FIG. 13, the signal at the logic level xe2x80x9cHxe2x80x9d on the data bus 6 flows from the output terminal 201 to the aluminum wiring 312, the P-diffusion area 307, the N-well area 301, the N-diffusion area 305, and to the aluminum wiring 311, in this order. As the aluminum wiring 311 is a power source wiring common to other MOS transistors, the signal at the logic level xe2x80x9cHxe2x80x9d is transmitted to those other MOS transistors that are connected to this aluminum wiring 311. This means that, in FIG. 13B, a high power source voltage Vcc is practically applied to the source of the other PMOS transistor 313 within the same N-well area 301.
In other words, there has been a problem that when the data bus 6 is at the logic level xe2x80x9cHxe2x80x9d, even when the power source voltage has not been supplied, the substantially high power source voltage Vcc is supplied to some transistors within the peripheral IC1, which results in an unnecessary power consumption and a leakage of the current.
FIG. 14A and FIG. 14B are diagrams for explaining a conventional example of a case where the power source terminal 200 is grounded by the power supply control unit when the power source voltage is not supplied to the peripheral IC1. In FIG. 14A and FIG. 14B, portions common to those in FIG. 13A and FIG. 13B are attached with the same legends, and their explanation will be omitted. In this example, there is a problem that when the data bus 6 is at the logic level xe2x80x9cHxe2x80x9d, the current flows directly from the output terminal 201 to the power source terminal 200, which also results in an unnecessary power consumption and a leakage of the current.
It is an object of the present invention to provide a semiconductor integrated circuit and a semiconductor integrated circuit system capable of completely turning OFF an NMOS transistor connected to an output terminal when a power source voltage is not supplied in a signal output circuit of a semiconductor integrated circuit, and also capable of completely separating a power source wiring for PMOS transistors that constitute the signal output circuit and that are connected to a power source terminal, from a power source wiring for other transistors that do not constitute the signal output circuit.
The semiconductor integrated circuit according to one aspect of the present invention comprises an output terminal and a signal output circuit. The output terminal is connected to an external circuit or is pulled by a first potential or a second potential. The signal output circuit comprises a first conductive type first MOS transistor that outputs a drain potential as output data to the output terminal, and an output terminal control unit that turns OFF the first MOS transistor according to a control signal.
According to the above invention, an N-type or P-type first conductive first MOS transistor having its drain connected to the output terminal is completely turned OFF according to a control signal. Therefore, even when the power supply to the semiconductor integrated circuit has been cut off, the first MOS transistor does not become in an unstable state. It becomes possible to prevent a leakage current from flowing to the first MOS transistor through the output terminal that has been driven by the first potential or the second potential or that has been pulled at the outside.
The semiconductor integrated circuit according to another aspect of the present invention comprises an output terminal, first and second power source terminals applied with a first potential or a second potential from the outside, and a signal output circuit. The output terminal is connected to an external circuit or is pulled by the first potential or the second potential. The signal output circuit comprises a MOS transistor that applies its drain potential as output data to the output terminal and has a potential of the first power source terminal applied to its source and that is formed in a well area independent of a well area of other MOS transistor to which a potential of the second power source terminal is applied.
According to the above invention, the MOS transistor that is connected to the output terminal in the signal output circuit and applies a voltage supplied from the first power source terminal to the source is formed in a well area independent of a well area of other MOS transistor. Therefore, it is possible to prevent a current from flowing from the output terminal that has been pulled up to a high power source voltage to other MOS transistor via the MOS transistor, for example, in a state that a power source voltage has not been supplied to the semiconductor integrated circuit.
The semiconductor integrated circuit according to still another aspect of the present invention comprises a plurality of output terminals, first and second power source terminals applied with a first potential or a second potential from the outside, and a plurality of signal output circuits. The plurality of output terminals are connected to an external circuit or are pulled by the first potential or the second potential. Each of the plurality of signal output circuits comprises a MOS transistor that applies its drain potential as output data to any one of the plurality of output terminals and has a potential of the first power source terminal applied to its source and that is formed in a well area independent of a well area of other MOS transistor to which a potential of the second power source terminal is applied.
According to the above invention, in each of the plurality of signal output circuits, a MOS transistor that is connected to any one of the plurality of output terminals and applies a power source voltage supplied from the first power source terminal to the source is formed in a well area independent of a well area of other MOS transistor. Therefore, it is possible to prevent a current from flowing from the output terminal that has been pulled up to a high power source voltage to other MOS transistor via the MOS transistor in a state that a power source voltage has not been supplied to the semiconductor integrated circuit.
The semiconductor integrated circuit according to still another aspect of the present invention comprises a bus, first and second power source terminals applied with a first potential or a second potential from the outside, and a plurality of functional circuits. All or a part of the plurality of functional circuits comprises a control terminal for inputting a control signal, an output terminal connected to the bus, a first power source input terminal connected to the first power source terminal, a second power source input terminal connected the second power source terminal, and a signal output circuit. The signal output circuit comprises a first conductive type first MOS transistor that outputs a drain potential as output data to the output terminal, a second conductive type second MOS transistor that has its drain connected to the first MOS transistor and has a potential of the first power source terminal applied to its source and that is formed in a well area independent of a well area of other MOS transistor to which a potential of the second power source terminal is applied, and an output terminal control unit that turns OFF the first MOS transistor when the control signal is active.
According to the above invention, in the signal output circuit of all or a part of the functional circuits, the first MOS transistor having its drain connected to the output terminal is completely turned OFF by the control signal. Further, the second MOS transistor that has its drain connected to the first MOS transistor and that has the power source voltage from the first power source terminal applied to its source is formed in a well area independent of a well area of other MOS transistor. Therefore, even when the power supply to the functional circuit has been cut off, the first MOS transistor does not become in an unstable state. It becomes possible to prevent a leakage current from flowing to the first MOS transistor through the output terminal from the bus that has been pulled up to a high power source voltage. It is also possible to prevent the leakage current from flowing to other MOS transistor via the second MOS transistor.
The semiconductor integrated circuit according to still another aspect of the present invention comprises a bus structured by a plurality of signal lines, first and second power source terminals applied with a first potential or a second potential from the outside, and a plurality of functional circuits. All or a part of the plurality of functional circuits comprises a control terminal for inputting a control signal, a plurality of output terminals connected to the signal lines of the bus at one to one, a first power source input terminal connected to the first power source terminal, and a plurality of signal output circuits. Each of the plurality of signal output circuits comprises a first conductive type first MOS transistor that outputs a drain potential as output data to any one of the plurality of output terminals, a second conductive type second MOS transistor that has its drain connected to the first MOS transistor and has a potential of the first power source terminal applied to its source and that is formed in a well area independent of a well area of other MOS transistor to which a potential of the second power source terminal is applied, and an output terminal control unit that turns OFF the first MOS transistor when the control signal is active.
According to the above invention, in each of the plurality of signal output circuits of all or a part of the functional circuits, the first MOS transistor having its drain connected to any one of the plurality of output terminals is completely turned OFF by the control signal. Further, the second MOS transistor that has its drain connected to the first MOS transistor and that has the power source voltage from the first power source terminal applied to its source is formed in a well area independent of a well area of other MOS transistor. Therefore, even when the power supply to the functional circuit has been cut off, the first MOS transistor does not become in an unstable state. It becomes possible to prevent a leakage current from flowing to the first MOS transistor through the output terminal from the bus that has been pulled up to a high power source voltage. It is also possible to prevent the leakage current from flowing to other MOS transistor via the second MOS transistor.
The semiconductor integrated circuit system according to still another aspect of the present invention comprises the above-described semiconductor integrated circuit, a power supply control unit for controlling a supply of a power source voltage to the semiconductor integrated circuit, and a control signal generating unit for making active the control signal and inputting the control signal to the output terminal control unit when the power source voltage has not been supplied to the semiconductor integrated circuit by the power supply control unit.
According to the above invention, the semiconductor integrated circuit system comprises the semiconductor integrated circuit, the power supply control unit, and the control signal generating unit. In this system, even when the power supply control unit has interrupted the supply of the power source voltage to the semiconductor integrated circuit, the MOS transistor that constitutes the signal output circuit in the semiconductor integrated circuit does not becomes in an unstable state. Thus, it is possible to prevent a leakage current from flowing to the MOS transistor through the output terminal that has been pulled up to a high power source voltage at the outside, for example.
The semiconductor integrated circuit system according to still another aspect of the present invention comprises the above-described semiconductor integrated circuit and a power supply control unit for controlling whether or not the first potential or the second potential is to be given to the first and second power source terminals in the semiconductor integrated circuit. The first and second power source terminals become in an open state when the first potential or the second potential is not given by the power supply control unit.
According to the above invention, the semiconductor integrated circuit system comprises the semiconductor integrated circuit and the power supply control unit. In this system, when a power source voltage has not been supplied to the semiconductor integrated circuit by the power supply control unit, the first and second power source terminals of the semiconductor integrated circuit become in a sate that they are not connected to the outside. Therefore, it is possible to make the first power source terminal and the second power source terminal independent of each other.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.